1. Field of the Invention
The present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device having an ODT (On Die Termination) function and a data processing system including the semiconductor device.
2. Description of Related Art
In a semiconductor device having plural chips arranged in parallel on an external bus, such as a DRAM (Dynamic Random Access Memory), a signal is occasionally reflected by chips having an output buffer in a high impedance state (Hi-Z). The signal quality on the external bus is degraded when such a reflection of a signal occurs. Therefore, a semiconductor device required to have a high data-transfer rate, such as a DDR2 SDRAM or a DDR3 SDRAM (Synchronous DRAM), often includes an ODT function that causes an output circuit to function as a terminating resistor.
When a semiconductor device has an ODT function, a terminating resistor is not required on a motherboard. Therefore, the number of parts can be reduced and reflections of signals can be prevented more effectively, and consequently the signal quality on the external bus can be improved.
An ODT operation is turned ON/OFF based on an external ODT signal supplied from outside of a semiconductor device. A period of time from when the external ODT signal is activated until when the ODT operation is turned ON is called “ODT latency (ODTL)”. While the value of the ODTL is fixed at two clock cycles in a DDR2 SDRAM, the value of the ODTL is defined by AL+CWL−2 in a DDR3 SDRAM. This arrangement is set because when the value of the ODTL is fixed at two clock cycles, a clock frequency improves and a clock cycle becomes short, resulting in a state where ON/OFF of the ODT operation is not quick enough. In this explanation, the “AL” represents an additive latency, and means an advanced input cycle of a column command, and the “CWL” means a clock cycle from an input of a write command to an input of write data.
For example, AL=0tCK, 3tCK to 13tCK, and CWL=5tCK to 10tCK in the DDR3 SDRAM. Therefore, the value of the ODTL is 3tCK to 21tCK, where “tCK” represents a clock cycle. In the DDR3 SDRAM, a latency width of the ODT becomes large and can be a very large value in the above manner. Therefore, a variable latency counter for the ODT needs to be provided inside of the DDR3 SDRAM.
Meanwhile, in the DDR3 SDRAM, the ODTL needs to be set at zero when entering in a slow power-down mode. When having entered in the slow power-down mode, an operation of a DLL circuit stops because of its reduced power consumption, and its latency cannot be correctly counted. Therefore, in a normal mode in which a DLL circuit is operating, an ODT operation is performed in a synchronous mode in which the ODTL is defined by AL+CWL−2. In the slow power-down mode in which the DLL circuit is stopped, an ODT operation is performed in an asynchronous mode. When returning from the slow power-down mode to the normal mode, an accurate ODT operation in the synchronous mode becomes possible after a lapse of a constant period to stabilize the operation of the DLL circuit. The constant period to stabilize the operation of the DLL circuit is called “tXPDLL”, and it is defined as 24 ns in DDR3 SDRAMs.
What is problematic is a case of shifting from a slow power-down mode to a normal mode while an external ODT signal is activated. In this case, because an ODT operation is switched from the asynchronous mode to the synchronous mode in the middle, the ODT becomes temporarily OFF depending on a circuit configuration although an ODT ON state should be maintained. Such cases occur when an ODT signal path for the synchronous mode and an ODT signal path for the asynchronous mode are provided and when an output from these signal paths is selected according to a mode, for example. For an internal ODT signal to pass through the ODT signal path for the synchronous mode, the lapse of the ODTL described above is necessary. Therefore, when a selection of an output is immediately switched from the ODT signal path for the asynchronous mode to the ODT signal path for the synchronous mode, the ODT operation is stopped in the middle thereof.
As a method of solving the above problems, there is a method described in Japanese Patent Application Laid-open No. 2007-115366. According to this proposed method, not only a counter that counts a latency of an ODT signal, but also a counter that counts a latency of a clock enable signal (an external signal designating an entry to and an exit from the slow power-down mode) is provided. When an asynchronous mode is shifted to a synchronous mode, a path is not immediately switched from an ODT signal path for the asynchronous mode to an ODT signal path for the synchronous mode, but the path is changed after waiting for an output of a counter that counts a latency of a clock enable signal. According to this method, even when the asynchronous mode is shifted to the synchronous mode, the ODT signal path for the synchronous mode becomes effective after an ODTL passes, and thus this method can prevent the ODT operation from being stopped in the middle thereof.
However, according to the above method, a counter that counts a latency of the clock enable signal is necessary in addition to the counter that counts a latency of the ODT signal. Therefore, the circuit scale becomes larger and the power consumption also becomes larger.
The above problems occur not only in DDR3 SDRAMs but also in common in semiconductor devices having a synchronous mode of activating an ODT synchronously with a clock signal and an asynchronous mode of activating an ODT asynchronously with a clock signal.